1. Field of the Invention
This invention relates to the field of integrated circuits and, in particular, to input buffers and reference circuits for integrated circuits. The invention consists of an adaptive active filtering method and apparatus that detects changes in noise conditions and reduces the active signal propagation speed as the noise conditions worsen. In addition, this filter uses a reference voltage generator which permits the circuit operation to be stabilized, when used in conjunction with other circuit elements that are normally used in the construction of functional circuits, by producing a reference voltage that varies in a controlled and specific fashion with changes in the noise conditions.
2. Background Art
Variations in MOS transistor conductance parameters, power supply voltages, and operating temperatures can increase or decrease the incidence of on-chip generated noise. Cold temperatures, high power supply voltages (i.e. V.sub.CC), and high transistor conductance parameters (i.e. fast transistors), are factors that lead to a high incidence of on-chip generated noise. Conversely, low noise conditions (i.e. high temperatures, low power supply voltages, and slow transistors) are conditions that are less conducive to an appreciable generation of noise.
On-chip generated noise is a major source of concern in the design of fast multi-output chips. For example, in the case of random access memories (i.e. RAMs), the simultaneous firing of the output drive transistors can generate a sufficiently large noise spike on the internal power supply busses to force the RAM to detect an incorrect address state, to write to the wrong memory cell, or to cause an access pushout while trying to recover the correct data state.
FIG. 1 shows one typical prior art input buffer consisting of a passive resistor and capacitor (RC) filter network. This prior art RC input buffer 1 is deficient in that the RC circuit requires substantial layout area and has a tendency to make the device performance a function of the input slew rate. Also, this filter is problematic because it cannot distinguish high on-chip noise conditions from low on-chip noise conditions (i.e. it is not an adaptive filter). Ideally, when high noise conditions are not present, an input noise filter should not have any effect on the device performance. However, since this filter is not adaptive, it performs the same delaying function irrespective of the probability of occurrence of on-chip generated noise. Consequently, during low noise conditions, this filter unnecessarily slows down the speed of the device.
A second prior art input buffer is shown in FIG. 2. This Schmitt-type positive feedback circuit configuration filters out input noise by introducing hysteresis in the signal path. Unfortunately, just as with the passive RC network of FIG. 1, the input buffer with hysteresis cannot distinguish between high and low noise conditions. Consequently, this buffer also adds a constant delay to the signal propagation path, since its filtering function is not modulated during low noise conditions.
In addition to the prior art input buffer noise control techniques, a second area of prior art is pertinent to the present invention. This area is the field of reference voltage generators, and FIG. 3 shows one prior art reference voltage generator. (A detailed description of this prior art generator is provided in U.S. Pat. No. 4,723,108 issued to Murphy et al., and this description is incorporated in this application by reference.) This reference voltage generator 3 consists of two cascaded voltage generator circuits 4 and 6, which use current control means (i.e. the current mirrors formed by transistors 10, 16, 12, and 8, and 22, 30, 20 and 26) to establish their respective output voltages (i.e. the voltages at nodes 14 and 28). The reference voltage that this generator produces is the output voltage 28 of the second voltage generator circuit 6.
Ideally, the generated noise filter reference voltage varies in a specific and controlled fashion with the changes in noise conditions. More specifically, the reference voltage characteristic curve (i.e. a curve that, for a specific operating temperature and transistor conductance parameters, shows the changes in the reference voltage with the changes in the power supply voltage) ideally consists of the following three parts: (1) a first linear voltage level corresponding to low noise conditions (in this embodiment, a low level); (2) a second linear voltage level corresponding to high noise conditions (in this embodiment, a high level); and (3) a knee (i.e., a region of maximum curvature) within the device operating range corresponding to intermediate noise conditions. The reference voltage's variance with noise conditions is controlled such that the characteristic curves vary in a controlled fashion with changes in transistor conductance parameters, operating temperatures, and supply voltage, in order to adequately track changes in the noise conditions.
Because of two reasons, prior art generator 3 of FIG. 3 does not always produce a reference voltage with the desired characteristics. First, this circuit's reference voltage characteristics do not vary substantially with respect to changes in on-chip noise conditions as a function of temperature. The use of temperature sensitive resistors 18 and 32 will further act to remove the desired temperature variance from the reference circuit's output. Temperature sensitive resistors are typically used: (1) since, in order to conserve layout area, the use of high sheet resistance materials is required, and (2) since, in order to insure accurate circuit operations, the resistors should not deviate more than 15% about their nominal value. Metal resistors require too large a layout area, polysilicon resistors do not have the required tolerance control, and doped well resistors vary greatly with biasing deviations. On the other hand, diffusion resistors meet both the resistance and tolerance constraints; however, they are temperature sensitive.
Diffusion resistors and transistors both have a positive temperature coefficients, which negate substantial temperature variation of the reference voltage since the resistance tracks in the same direction as the transistor channel on resistance. Consequently, as FIG. 4 shows, the circuit presented in FIG. 3 produces reference voltage characteristic curves which do not sufficiently vary with respect to changes in the temperature. In other words, this prior art reference voltage generator does not adequately respond to temperature variations in the amount of on-chip generated noise.
Second, due to variation between the NMOS and PMOS transistor conductance parameters (i.e. process variations), the circuit presented in FIG. 3 suffers from significant destabilization of the desired reference voltage characteristics. These process variations create different permutations of CMOS technology, of which a few are: (1) typical PMOS transistors and typical NMOS transistors (i.e. TT process); (2) fast PMOS transistors and fast NMOS transistors (i.e. FF process); (3) fast PMOS transistors and slow NMOS transistors (i.e. FS process); (4) slow PMOS transistors and fast NMOS transistors (i.e. SF process); and (5) slow PMOS transistors and slow NMOS transistors (i.e. SS process).
Whenever the generator of FIG. 3 comprises non-typical transistors, the reference voltage characteristic curves do not vary in the desired specific and controlled fashion with the changes in noise conditions. The characteristic curves are non-ideal because variations in transistor conductance parameters change the node voltages in the two cascaded voltage generator circuits. Node 14 in FIG. 3 serves as a good example to demonstrate this change in node voltages. If typical CMOS (i.e. TT process) transistors are used, the node voltage at 14 is at its nominally designed value. However, if non-typical CMOS transistors are used, the voltage at node 14 differs from its optimum level. For example, if slow P-channels and fast N-channels (SF process corner) are used, the voltage at node 14 will be lower than its nominally designed value. This node voltage will be pulled down, because the channel resistance of NMOS transistor 16 is less than the channel resistance of PMOS transistor 12. This voltage level decrease at the output of the first voltage generator circuit, in turn causes a voltage level decrease at the output of the second voltage generator circuit. The output of the second voltage generator circuit decreases because the reduced voltage at node 14 increases the drive of PMOS transistor 20 (i.e. increases V.sub.GS) which in turn strengthens the NMOS transistor 30. In addition, a second pull down occurs at the output of the second voltage generator circuit (i.e. at node 28), since the channel resistance of NMOS transistor 30 has decreased with respect to the channel resistance of PMOS transistors 24 and 26. Thus, the voltage at the output of the second voltage generator circuit is pulled below its nominal value (i.e. the output voltage when typical-typical transistors are used).
Finally, FIG. 5 shows the characteristic curves of the prior art reference voltage generator for varying values of transistor conductance skew; it should be noted that, in order to best show the destabilization of the reference voltage due to process variations, temperature insensitive resistors were used. As it can be seen from these curves, the variations in transistor conductance parameters will destabilize the location of the characteristic curve's knee (i.e. region of maximum curvature). The high operating temperature, slow P-channel, slow N-channel (SS process corner) curve presents one example of this generator's undesirable output voltage characteristics, since this curve does not have a knee within the device operating range.